Programming and Development

Half Adder module half_adder ( A,B,S,C ); output S ; output C ; input A ; input B ; assign S = A ^ B; assign C = A & B; endmodule Testbench module halfadder_tb; wire t_s,t_c;   reg t_a, t_b; orgate my_gate( .a(t_a), .b(t_b), .s(t_s), .c(t_c)); i nitial begin   $monitor (t_a, t_b, t_s,t_c);   t_a = 1'b0; t_b = 1'b0; #5 t_a = 1'b0; t_b = 1'b1; #5 t_a = 1'b1; t_b = 1'b0; #5 t_a = 1'b1; t_b = 1'b1; end endmodule

//assume a and b are inputs and y is output module orgate (a, b, y); input a, b; output y; assign y = a & b; endmodule   TestBench   module orgate_tb;   wire t_y; reg t_a, t_b; orgate my_gate( .a(t_a), .b(t_b), .y(t_y) ); i nitial begin   $monitor (t_a, t_b, t_y);   t_a = 1'b0;   t_b = 1'b0;   #5   t_a = 1'b0;   t_b = 1'b1;   #5   t_a = 1'b1;   t_b = 1'b0; #5   t_a = 1'b1;   t_b = 1'b1; end endmodule  

VHDL code for Full adder using half adder                       half_adder.vhdl ENTITY half_adder IS --- Half Adder PORT(A,B: IN BIT ; S, Cout : OUT BIT); END full_adder; ARCHITECTURE half_adder_beh OF half_adder IS BEGIN S <= A xor B; Cout <= A and B; END full_adder_beh;   or_gate.vhdl ENTITY or_gate IS PORT(A,B: IN BIT ; C : OUT BIT); END or_gate; ARCHITECTURE or_gate_beh OF or_gate IS BEGIN C <= A or B; END or_gate_beh;     full_adder.vhdl ENTITY full_adder IS --- Full Adder PORT(A,B,Cin: IN BIT ; S, C : OUT BIT); END full_adder;  ARCHITECTURE str OF full_adder IS --component Declaration Component half_adder IS PORT(A,B: IN BIT ; S, Cout : OUT BIT); END Component; Component or_gate IS PORT(A,B: IN BIT ; C : OUT BIT); END Component; signal s1,c2,c3:std_logic;  BEGIN X1: half_adder port map(A,B,s1,c1); X2: half_adder port map(s1,Cin,S,c2);   X3: or_gate port

VHDL code for Full Adder With Test bench   The full - adder circuit adds three one-bit binary numbers (C A B) and outputs two one-bit binary numbers, a sum (S) and a carry (C1). The full - adder is usually a component in a cascade of adders , which add 8, 16, 32, etc. binary numbers.                        ENTITY full_adder IS --- Full Adder PORT(A,B,Cin: IN BIT ; S, Cout : OUT BIT); END full_adder; ARCHITECTURE full_adder_beh OF full_adder IS BEGIN PROCESS(A,B,Cin) -- Sensitive on all the three bits VARIABLE temp :BIT; BEGIN --- DOES the addition in one DELTA time temp := A XOR B; S <= temp XOR Cin; Cout <= (A AND B) OR (temp AND Cin); END PROCESS ; END full_adder_beh;   Test Bench LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY Testbench_full_adder IS END Testbench_full_adder; ARCHITECTURE behavior OF Testbench_full_adder IS -- Component Declaration for the

Half Adder Half adder is a combinational  arithmetic circuit that adds two numbers and produces a sum bit (S) and carry bit (C) as the output. If  A and B are the input bits, then sum bit (S) is the X-OR of A and B  and the carry bit (C) will be the AND of A and B. From this it is clear that a half adder circuit can be easily constructed using one X-OR gate and one AND gate. Half adder is the simplest of all adder circuit, but it has a major disadvantage.  The half adder can add only two input bits (A and B) and has nothing to do with the carry if there is any in the input. So if the input to a half adder have a carry, then it will be neglected it and adds only the A and B bits. That means the binary addition process is not complete and that’s why it is called a half adder. The truth table, schematic representation and XOR//AND realization of a half adder are shown in the figure below. CODE ENTITY half_adder IS --- Half Adder PORT(a,b:in std_logic; s,c :OUT

VHDL code for OR gate with Test bench   library IEEE; use IEEE.std_logic_1164.all; entity orgate is Port( A : in std_logic; B : in std_logic; Y : out std_logic ); end orgate; architecture Behavioral of orgate is begin Y<= A  or B ; end Behavioral; Test Bench library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity or_tb is -- Port ( ); end or_tb; architecture Behavioral of or_tb is --Component name and entity's name must be same --ports must be same  component orgate is Port (A,B:in std_logic; C: out std_logic ); end component; --inputs signal a: std_logic:= '0'; signal b: std_logic:= '0'; --outputs signal c : std_logic; begin uut: orgate PORT MAP(a=>A,b=>B,c=>C); --Stimulus Process stim_proc:process begin wait for 10ns; a<='1'; b<='0'; wait for 10ns; a<='0'; b<='1'; wait for 10ns; a<='0'; b<='0'; wait for 10ns; a<='1'; b<=

VHDL Code for AND gate With Test Bench     li brary IEEE; use IEEE.std_logic_1164.all; entity andgate is Port( A : in std_logic; B : in std_logic; Y : out std_logic ); end andgate; architecture Behavioral of andgate is begin Y<= A and B ; end Behavioral; Test Bench library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity and_tb is -- Port ( ); end and_tb; architecture Behavioral of and_tb is --Component name and entity's name must be same --ports must be same  component andgate is Port (A,B:in std_logic; C: out std_logic ); end component; --inputs signal a: std_logic:= '0'; signal b: std_logic:= '0'; --outputs signal c : std_logic; begin uut: andgate PORT MAP(a=>A,b=>B,c=>C); --Stimulus Process stim_proc:process begin wait for 10ns; a<='1'; b<='0'; wait for 10ns; a<='0'; b<='1'; wait for 10ns; a<='0'; b<='0'; wait for 10ns; a<='