Programming and Development

//assume a and b are inputs and y is output module orgate (a, b, y); input a, b; output y; assign y = a & b; endmodule   TestBench   module orgate_tb;   wire t_y; reg t_a, t_b; orgate my_gate( .a(t_a), .b(t_b), .y(t_y) ); i nitial begin   $monitor (t_a, t_b, t_y);   t_a = 1'b0;   t_b = 1'b0;   #5   t_a = 1'b0;   t_b = 1'b1;   #5   t_a = 1'b1;   t_b = 1'b0; #5   t_a = 1'b1;   t_b = 1'b1; end endmodule  

VHDL code for Full adder using half adder                       half_adder.vhdl ENTITY half_adder IS --- Half Adder PORT(A,B: IN BIT ; S, Cout : OUT BIT); END full_adder; ARCHITECTURE half_adder_beh OF half_adder IS BEGIN S <= A xor B; Cout <= A and B; END full_adder_beh;   or_gate.vhdl ENTITY or_gate IS PORT(A,B: IN BIT ; C : OUT BIT); END or_gate; ARCHITECTURE or_gate_beh OF or_gate IS BEGIN C <= A or B; END or_gate_beh;     full_adder.vhdl ENTITY full_adder IS --- Full Adder PORT(A,B,Cin: IN BIT ; S, C : OUT BIT); END full_adder;  ARCHITECTURE str OF full_adder IS --component Declaration Component half_adder IS PORT(A,B: IN BIT ; S, Cout : OUT BIT); END Component; Component or_gate IS PORT(A,B: IN BIT ; C : OUT BIT); END Component; signal s1,c2,c3:std_logic;  BEGIN X1: ha...