Programming and Development

//assume a and b are inputs and y is output module orgate (a, b, y); input a, b; output y; assign y = a & b; endmodule   TestBench   module orgate_tb;   wire t_y; reg t_a, t_b; orgate my_gate( .a(t_a), .b(t_b), .y(t_y) ); i nitial begin   $monitor (t_a, t_b, t_y);   t_a = 1'b0;   t_b = 1'b0;   #5   t_a = 1'b0;   t_b = 1'b1;   #5   t_a = 1'b1;   t_b = 1'b0; #5   t_a = 1'b1;   t_b = 1'b1; end endmodule  

Circuit Diagram With TT   module andgate (a, b, y); input a, b; output y; assign y = a & b; endmodule   TestBench   module andgate_tb;   wire t_y; reg t_a, t_b; andgate my_gate( .a(t_a), .b(t_b), .y(t_y) ); i nitial begin $monitor (t_a, t_b, t_y); t_a = 1'b0; t_b = 1'b0; #5 t_a = 1'b0; t_b = 1'b1; #5 t_a = 1'b1; t_b = 1'b0; #5 t_a = 1'b1; t_b = 1'b1; end endmodule