Verilog code for OR gate with testbench






//assume a and b are inputs and y is output
module orgate (a, b, y);
input a, b;
output y;

assign y = a & b;

endmodule
 

TestBench  

module orgate_tb;
 wire t_y;
 reg t_a, t_b;
 orgate my_gate( .a(t_a), .b(t_b), .y(t_y) );
 initial begin     
$monitor(t_a, t_b, t_y); 
t_a = 1'b0; 
t_b = 1'b0;  
#5 
t_a = 1'b0; 
t_b = 1'b1; 
#5  
t_a = 1'b1; 
t_b = 1'b0; #5 
t_a = 1'b1; 
t_b = 1'b1;
end
endmodule
 



Comments

  1. Unknown22 February 2019 at 11:28

    Why we use #5

    ReplyDelete
    Replies
    1. Unknown8 September 2020 at 08:25

      #5 means 5 seconds . the value of the variable a/(b) keeps switching between hign and low after every 5 seconds. hope u got it now.

      Delete
  2. Bhanu Prakash22 July 2019 at 21:45

    This is and program

    ReplyDelete

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