Programming and Development

Half Adder module half_adder ( A,B,S,C ); output S ; output C ; input A ; input B ; assign S = A ^ B; assign C = A & B; endmodule Testbench module halfadder_tb; wire t_s,t_c;   reg t_a, t_b; orgate my_gate( .a(t_a), .b(t_b), .s(t_s), .c(t_c)); i nitial begin   $monitor (t_a, t_b, t_s,t_c);   t_a = 1'b0; t_b = 1'b0; #5 t_a = 1'b0; t_b = 1'b1; #5 t_a = 1'b1; t_b = 1'b0; #5 t_a = 1'b1; t_b = 1'b1; end endmodule

Circuit Diagram With TT   module andgate (a, b, y); input a, b; output y; assign y = a & b; endmodule   TestBench   module andgate_tb;   wire t_y; reg t_a, t_b; andgate my_gate( .a(t_a), .b(t_b), .y(t_y) ); i nitial begin $monitor (t_a, t_b, t_y); t_a = 1'b0; t_b = 1'b0; #5 t_a = 1'b0; t_b = 1'b1; #5 t_a = 1'b1; t_b = 1'b0; #5 t_a = 1'b1; t_b = 1'b1; end endmodule  

VHDL code for Full Adder With Test bench   The full - adder circuit adds three one-bit binary numbers (C A B) and outputs two one-bit binary numbers, a sum (S) and a carry (C1). The full - adder is usually a component in a cascade of adders , which add 8, 16, 32, etc. binary numbers.                        ENTITY full_adder IS --- Full Adder PORT(A,B,Cin: IN BIT ; S, Cout : OUT BIT); END full_adder; ARCHITECTURE full_adder_beh OF full_adder IS BEGIN PROCESS(A,B,Cin) -- Sensitive on all the three bits VARIABLE temp :BIT; BEGIN --- DOES the addition in one DELTA time temp := A XOR B; S <= temp XOR Cin; Cout <= (A AND B) OR (temp AND Cin); END PROCESS ; END full_adder_beh;   Test Bench LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY Testbench_full_adder IS EN...

VHDL Code for AND gate With Test Bench     li brary IEEE; use IEEE.std_logic_1164.all; entity andgate is Port( A : in std_logic; B : in std_logic; Y : out std_logic ); end andgate; architecture Behavioral of andgate is begin Y<= A and B ; end Behavioral; Test Bench library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity and_tb is -- Port ( ); end and_tb; architecture Behavioral of and_tb is --Component name and entity's name must be same --ports must be same  component andgate is Port (A,B:in std_logic; C: out std_logic ); end component; --inputs signal a: std_logic:= '0'; signal b: std_logic:= '0'; --outputs signal c : std_logic; begin uut: andgate PORT MAP(a=>A,b=>B,c=>C); --Stimulus Process stim_proc:process begin wait for 10ns; a<='1'; b<='0'; wait for 10ns; a<='0'; b<='1'; wait for 10ns; a<='0'; b<='0'; wait for 10ns; a<='...