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Showing posts from October, 2017

Verilog code for Half Adder with Testbench

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Half Adder module half_adder ( A,B,S,C ); output S ; output C ; input A ; input B ; assign S = A ^ B; assign C = A & B; endmodule Testbench module halfadder_tb; wire t_s,t_c;   reg t_a, t_b; orgate my_gate( .a(t_a), .b(t_b), .s(t_s), .c(t_c)); i nitial begin   $monitor (t_a, t_b, t_s,t_c);   t_a = 1'b0; t_b = 1'b0; #5 t_a = 1'b0; t_b = 1'b1; #5 t_a = 1'b1; t_b = 1'b0; #5 t_a = 1'b1; t_b = 1'b1; end endmodule

Verilog code for OR gate with testbench

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//assume a and b are inputs and y is output module orgate (a, b, y); input a, b; output y; assign y = a & b; endmodule   TestBench   module orgate_tb;   wire t_y; reg t_a, t_b; orgate my_gate( .a(t_a), .b(t_b), .y(t_y) ); i nitial begin   $monitor (t_a, t_b, t_y);   t_a = 1'b0;   t_b = 1'b0;   #5   t_a = 1'b0;   t_b = 1'b1;   #5   t_a = 1'b1;   t_b = 1'b0; #5   t_a = 1'b1;   t_b = 1'b1; end endmodule  

How to install Android Studio

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Android Studio : Installation and setup Android Studio is the official Integrated Development Environment (IDE) for Android app development, based on IntelliJ IDEA . On top of IntelliJ's powerful code editor and developer tools, Android Studio offers even more features that enhance your productivity when building Android apps, such as: A flexible Gradle-based build system A fast and feature-rich emulator A unified environment where you can develop for all Android devices Instant Run to push changes to your running app without building a new APK Code templates and GitHub integration to help you build common app features and import sample code Extensive testing tools and frameworks Lint tools to catch performance, usability, version compatibility, and other problems C++ and NDK support Built-in support for Google Cloud Platform , making it easy to integrate Google Cloud Messaging and App Engine System Requirements for installation Windows Microsoft® Windows® 7/8/...

Verilog code for AND gate with test bench

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Circuit Diagram With TT   module andgate (a, b, y); input a, b; output y; assign y = a & b; endmodule   TestBench   module andgate_tb;   wire t_y; reg t_a, t_b; andgate my_gate( .a(t_a), .b(t_b), .y(t_y) ); i nitial begin $monitor (t_a, t_b, t_y); t_a = 1'b0; t_b = 1'b0; #5 t_a = 1'b0; t_b = 1'b1; #5 t_a = 1'b1; t_b = 1'b0; #5 t_a = 1'b1; t_b = 1'b1; end endmodule  

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